The present invention is directed to a threedimensional, one-transistor cell arrangement for dynamic semiconductor memories. The capacitor, for the charges to be stored, is created as a trench capacitor in the substrate. The first electrode is formed by the substrate and the second electrode, that stores the charges, is formed by doped polycrystalline silicon that fills the trench. The capacitor, separated by an insulating layer, is arranged under the field effect transistor (selection transistor). An insulated gate electrode (transfer electrode/word line), that lies at the surface of the substrate, is arranged having source/drain zones generated in the recrystallized silicon layer applied on the insulating layer and is connected to the source/drain zones thereof via an electrically conductive contact.
Such an arrangement can be derived from, for example, European patent application No. 0 167 764. Such an arrangement is also disclosed in a report by M. Ohkura et al, "A Three-Dimensional DRAM Cell of Stacked Switching-Transistor in SOI", in IEDM Digest of Technical Papers; SOI technique refers to what is known as the silicon on insulator technique.
One-transistor cell/trench capacitor arrangements can also be derived from European patent application Nos. 0 234 384 and 0 1O8 390. These do not disclose, however, the SOI technique.
What all of these arrangements have in common is that the capacitor is executed as a trench cell in order to increase the packing density in dynamic memories (DRAMs). This is due to the smaller cell areas available and because of the capacitance quantities from 30 through 50 fF required for noise protection.
The utilization of the third dimension in the trench cell provides the possibility of realizing a cell capacitance of 40 fF given a minimum space requirement.
By introduction of the silicon on insulator technique, as disclosed in the report by Ohkura, the soft error sensitivity is reduced and a small area requirement on the order of magnitude of 5 .mu.m.sup.2 is realizable.